Semiconductor processing technology nowadays allows complex systems to be integrated on one single chip. A consistent system design technology is in great need to cope with such complexity and with the ever shortening time-to-market requirements (B. Tuck Raise your sights to the system level—design report: '97 Paris forum (round-table discussion). Computer Design, pp. 53-74, June 1997.). It should allow to map these applications cost-efficiently to the target realisation while meeting all real-time and other constraints.
The target applications of our task-level system synthesis approach are advanced real-time multi-media and information processing (RMP) systems, such as consumer multi-media electronics and personal communication systems. These applications involve a combination of complex data- and control-flow where complex data types are manipulated and transferred. Most of these applications are implemented with compact and portable devices, putting stringent constraints on the degree of integration (i.e. chip area) and on their power consumption. Secondly, these systems are extremely heterogeneous in nature and combine high performance data processing (e.g. data processing on transmission data input) as well as slow rate control processing (e.g. system control functions), synchronous as well as asynchronous parts, analog versus digital, and so on. Thirdly, time-to-market has become a critical factor in the design phase. Finally, these systems are subjected to stringent real-time constraints (both hard and soft deadlines are present), complicating their implementation considerably.
The platform for these applications include one or more programmable components, augmented with some specialized data paths or co-processors (accelerators). The programmable components run software components, being slow to medium speed algorithms, while time-critical parts are executed on dedicated hardware accelerators.
When looking at contemporary design practices for mapping software (and hardware) on such a platform, one can only conclude that these systems nowadays are designed in a very ad hoc manner (F. Thoen, F. Catthoor, “Modeling, Verification and Exploration of Task-level Concurrency in Real-Time Embedded Systems,” ISBN 0-7923-7737-0, Kluwer Acad. Publ., Boston, 1999.) The design trajectory starts by identifying the global specification entities that functionally belong together, called tasks or processes. This step is followed by a manual ‘hardware-software partitioning’. Because of separate implementation of the different tasks and of the software and hardware, afterwards a system integration step is inevitable. This manual step performs the ‘system/software embedding’ and synthesizes the interface hardware, which closes the gap between the software and the hardware component.
The main goal of system/software embedding is to encapsulate the concurrent tasks in a control shell which takes care of the task scheduling (software scheduling in the restricted sense) and the inter-task communication. Task scheduling is an error-prone process that requires computer assistance to consider the many interactions between constraints. Unfortunately, current design practices for reactive real-time systems are ad hoc and not very retargetable. Designers have used real-time operating systems (RTOS) or kernels to solve some of these scheduling problems. Both of RTOSs and kernels assume a specific processor and a particular I/O configuration. Such practices result in poor modularity and limited retargetability, thus severely discourage exploitation of the co-design space. This is the case even if the program is written in a high-level language. Moreover, these RTOSs in fact only provide limited support for real-timeness, and leave satisfaction of the timing constraints to the designer. They can be considered as nothing more than an optimized back-end for performing the task scheduling, and typically they are not integrated in a design framework in which a global specification model serves as entry point.
Existing approaches we will work neither at the detailed white-box task model (see e.g. P. Eles, K. Kuchcinski, Z. Peng, A. Doboli, P. Pop, “Scheduling of conditional process graphs for the synthesis of embedded systems,” Proc. 1st ACM/IEEE Design and Test in Europe Conf., Paris, France, pp. 132-138, February 1998. P. Hoang, J. Rabaey, “Scheduling of DSP programs onto multiprocessors for maximum throughput,” IEEE Trans. on Signal Processing, Vol. SP-41, No. 6, pp. 2225-2235, June 1993.) where all the operations are considered already during the mapping and where too much information is present to allow a thorough exploration, nor at the black-box task model (see e.g. S. Ha, E. Lee, “Compile-time scheduling of dynamic constructs in dataflow program graphs,” IEEE Trans. on Computers, Vol. C-47, No. 7, pp. 768-778, July 1997. I. Hong, M. Potkonja, M. Srivastava, “On-line scheduling of hard real-time tasks on variable voltage processor,” Proc. IEEE Int. Conf. on Comp. Aided Design, Santa Clara Calif., pp. 653-656, November 1998. Y. Li, W. Wolf, “Scheduling and allocation of single-chip multi-processors for multimedia,” Proc. IEEE Wsh. on Signal Processing Systems (SIPS), Leicester, UK, pp. 97-106, November 1997. where insufficient information is available to accurately steer even the most crucial cost trade-offs.
Other work P. Eles, K. Kuchcinski, Z. Peng, A. Doboli, P. Pop, “Scheduling of conditional process graphs for the synthesis of embedded systems,” Proc. 1st ACM/IEEE Design and Test in Europe Conf., Paris, France, pp. 132-138, February 1998.) considers task scheduling as a separate issue from cost. In their work, the assignment to processors with different power or varying supply voltage is either “automatic,” i.e., without trade-off between timing and cost, e.g., the processor energy costs, or not treated.